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USB2224
Bus Powered USB2.0 Flash Media Controller
Datasheet
Product Features
Complete System Solution for interfacing SmartMediaTM (SM) or xD Picture CardTM (xD), Memory StickTM (MS), High Speed Memory Stick (HSMS), Memory Stick PRO (MSPRO), MS DuoTM, Secure Digital (SD), Mini-Secure Digital (Mini-SD), Transflash (SD), MultiMediaCardTM (MMC), Reduced Size Multimedia Card (RSMMC), NAND Flash, Compact FlashTM (CF), CF UltraTM I & II and CF form-factor ATA hard drives to USB2.0 bus.
- Supports USB Bulk Only Mass Storage Compliant Bootable BIOS
Double Buffered Bulk Endpoint
- Bi-directional 512 Byte Buffer for Bulk Endpoint - 64 Byte RX Control Endpoint Buffer - 64 Byte TX Control Endpoint Buffer
Internal or External Program Memory Interface
- 64K Byte Internal Code Space or Optional 64K Byte External Code Space using Flash, SRAM or EPROM memory.
On Board 12Mhz Crystal Driver Circuit On-Chip 1.8V Regulator for Low Power Core Operation Internal PLL for 480Mhz USB2.0 Sampling, Configurable MCU clock Supports firmware upgrade via USB bus if "boot block" Flash program memory is used 15 GPIOs for special function use: LED indicators, button inputs, power control to memory devices, etc.
- Inputs capable of generating interrupts with either edge sensitivity - Attribute bit controlled features: - Activity LED polarity/operation/blink rate - Full or Partial Card compliance checking - Bus or Self Powered - LUN configuration and assignment - Write Protect Polarity - Detach on no Card Inserted for Notebook apps - Cover Switch operation for xD compliance - Inquiry Command operation - SD Write Protect operation - Older CF card support - Force USB 1.1 reporting
Support for simultaneous operation of all above devices. (only one at a time of each of the following groups supported: CF or ATA drive, SM or XD or NAND, SD or MMC) On-Chip 4-Bit High Speed Memory Stick and MS PRO Hardware Circuitry On-Chip firmware reads and writes High Speed Memory Stick and MS PRO 1-bit ECC correction performed in hardware for maximum efficiency USB Bus Power Certified 3.3 Volt I/O with 5V input tolerance Complete USB Specification 2.0 Compatibility for Bus Powered Operation
- Includes USB2.0 Transceiver - A Bi-directional Control and a Bi-directional Bulk Endpoint are provided.
8051 8 bit microprocessor
- Provides low speed control functions - 30 Mhz execution speed at 4 cycles per instruction average - 12K Bytes of internal SRAM for general purpose scratchpad - 768 Bytes of internal SRAM for general purpose scratchpad or program execution while re-flashing external ROM
Compatible with Microsoft WinXP, WinME, Win2K SP3, Apple OS10, Softconnex, and Linux Multi-LUN Mass Storage Class Drivers Win2K, Win98/98SE and Apple OS8.6 and OS9 Multi-LUN Mass Storage Class Drivers available from SMSC 128 Pin TQFP Package (1.0mm height, 14mm x14mm footprint); PB free package also available
SMSC USB2224
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DATASHEET
Bus Powered USB2.0 Flash Media Controller Datasheet
ORDERING INFORMATION
Order Number(s): USB2224-NE-02 for 128 pin TQFP package USB2224-NU-02 for 128 pin PB Free TQFP package
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) SMSC 2004. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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SMSC USB2224
DATASHEET
Bus Powered USB2.0 Flash Media Controller Datasheet
Table of Contents
Chapter 1 Chapter 2
2.1 2.2 3.1 3.2
General Description ............................................................................................................. 4 Acronyms and Definitions ................................................................................................... 5
Acronyms ............................................................................................................................................ 5 Definitions............................................................................................................................................ 5
Chapter 3
3.2.1
Pin Table ............................................................................................................................... 6
128 Pin TQFP...........................................................................................................................................7
128-Pin Package ................................................................................................................................. 6 128 Pin List Table................................................................................................................................ 7
Chapter 4
4.1
Pin Configuration................................................................................................................. 8 Block Diagram...................................................................................................................... 9 Pin Descriptions.................................................................................................................. 10
128 Pin TQFP...................................................................................................................................... 8
Chapter 5 Chapter 6
6.1 6.2 6.3 7.1 7.2
Pin Descriptions ................................................................................................................................ 10 Buffer Type Descriptions ................................................................................................................... 15 GPIO Usage Table ............................................................................................................................ 15
Chapter 7
DC Parameters ................................................................................................................... 17
Maximum Guaranteed Ratings ......................................................................................................... 17 DC Electrical Characteristics............................................................................................................. 17
Chapter 8
Package Outline.................................................................................................................. 20
List of Figures
Figure 8.1 - 128 Pin TQFP Package ............................................................................................................................20
List of Tables
Table 3.1 - Pinout...........................................................................................................................................................6 Table 6.1 - Pin Description ...........................................................................................................................................10 Table 6.2 - USB2224 Buffer Type Descriptions ............................................................................................................15 Table 6.3 - GPIO Usage...............................................................................................................................................15 Table 8.1 - 128 Pin TQFP Package Parameters ..........................................................................................................20
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Bus Powered USB2.0 Flash Media Controller Datasheet
Chapter 1
General Description
The USB2224 is a USB2.0 Bulk Only Mass Storage Class Peripheral Controller intended for supporting CompactFlash (CF and CF Ultra I/II) in True IDE Mode only, SmartMedia (SM) and XD cards, Memory Stick (MS), Memory Stick DUO (MSDUO) and Memory Stick Pro (MSPRO), Secure Digital (SD), and MultiMediaCard (MMC) flash memory devices. It provides a single chip solution for the most popular flash memory cards in the market. The device consists of a USB2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad, and program SRAM, and CF, MS, SM and SD controllers. The SD controller supports both SD and MMC devices. Provisions for external Flash Memory up to 64K bytes for program storage is provided. 12K bytes of scratchpad SRAM and 768 Bytes of program SRAM are also provided. Fifteen GPIO pins are provided for indicators, external serial EEPROM for OEM id and system configuration information, and other special functions. The internal ROM program is capable of implementing any combination of single or multi-LUN CF/SD/MMC/SM/MS reader functions with individual card power control and activity indication. SMSC also provides licenses** for Win98 and Win2K drivers and setup utilities. Note: Please check with SMSC for precise features and capabilities for the current ROM code release.
*Note: In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other intellectual property rights from or through various persons or entities, including without limitation media standard companies, forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations include without limitation the following: Sony Corporation (Memory Stick, Memory Stick Pro); SD3 LLC (Secure Digital); MultiMedia Card Association (MultiMediaCard); the SSFDC Forum (SmartMedia); the Compact Flash Association (Compact Flash); and Fuji Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation (xD-Picture Card). SMSC does not make such licenses or technical information available; does not promise or represent that any such licenses or technical information will actually be obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or otherwise with respect to, any such technical information. SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future patents related to solid state disk or other flash memory technology or applications ("Solid State Disk Patents"). By making any purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of the customer's rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no obligation for any costs or expenses related to the customer's obtaining or having obtained rights or licenses under any Solid State Disk Patents. SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE. No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask work right, trade secret, or other intellectual property right. **To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of these Software License Agreements may be obtained by contacting SMSC.
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Bus Powered USB2.0 Flash Media Controller Datasheet
Chapter 2
2.1
Acronyms and Definitions
Acronyms
SM: FM: CF: SD: SmartMedia Flash Media Compact Flash Secure Digital SMC: SmartMedia Controller FMC: Flash Media Controller CFC: CompactFlash Controller SDC: Secure Digital Controller MMC: MultiMediaCard MS: Memory Stick MSC: Memory Stick Controller TPC: Transport Protocol Code. ECC: Error Checking and Correcting CRC: Cyclic Redundancy Checking XD: XD Picture Card
2.2
Definitions
Flash Media DMA UNIT (FMDU): The control logic in the flash media controller block as shown in the Block Diagram that support the data transfer from CFC, SMC, MSC and SDC to EP2 buffer directly. SD/MMC: the built-in SD controller (SDC) supports both SD and MMC devices. Flash Media Controller Data Multiplexer (FMC DATA MUX): The multiplexer to enable the different data path from the different flash media controllers (CFC, SMC, MSC and SDC).
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Chapter 3
3.1
CF_D0 CF_D4 CF_D8 CF_D12 CF_nIOR CF_IORDY CF_SA1 SM_D0 SM_D4 SM_ALE SM_nWP SM_nWPS MS_BS MS_D1 SD_CMD SD_DAT2 USB+ VDDP VREG MA0 MA4 MA8 MA12 MD0 MD4 nMRD nRESET GPIO4 GPIO8 GPIO12 nTEST0 (3)VDDIO
Pin Table
Table 3.1 - Pinout CompactFlash INTERFACE (28 Pins) CF_D1 CF_D2 CF_D5 CF_D6 CF_D9 CF_D10 CF_D13 CF_D14 CF_nIOW CF_IRQ CF_nCS0 CF_nCS1 CF_SA2 CF_nCD1 SmartMedia / XD INTERFACE (17 Pins) SM_D1 SM_D2 SM_D5 SM_D6 SM_CLE SM_nRE SM_nB/R SM_nCE Memory Stick INTERFACE (7 Pins) MS_SDIO/MS_D0 MS_SCLK MS_D2 MS_D3 SD INTERFACE (7 Pins) SD_CLK SD_DAT0 SD_DAT3 SD_nWP USB INTERFACE (13 Pins) USBATEST VSSP (2)VDDA XTAL1/CLKIN XTAL2 MEMORY/IO INTERFACE (27 Pins) MA1 MA2 MA5 MA6 MA9 MA10 MA13 MA14 MD1 MD2 MD5 MD6 nMWR nMCE MISC (18 Pins) GPIO1 GPIO2 GPIO5 GPIO6/ROMEN GPIO9 GPIO10 GPIO13 GPIO14 nTEST1 DIGITAL, POWER, GROUND & NC (11 Pins) (4)VSSIO (2)VDDCORE Total 128 CF_D3 CF_D7 CF_D11 CF_D15 CF_nRESET CF_SA0 CF_nCD2 SM_D3 SM_D7 SM_nWE SM_nCD
128-Pin Package
MS_INS
SD_DAT1
RBIAS (2)VSSA
MA3 MA7 MA11 MA15 MD3 MD7
GPIO3 GPIO7 GPIO11 GPIO15
(2)VSSCORE
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Bus Powered USB2.0 Flash Media Controller Datasheet
3.2
3.2.1
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
128 Pin List Table
128 Pin TQFP
MA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PIN # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME MS_D2 MS_D1 MS_D0 MS_SCLK MS_BS SD_nWP VDDIO SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 SD_CMD SD_CLK CF_D0 CF_D1 CF_D2 CF_D3 CF_D4 VSSIO VSSCORE CF_D5 CF_D6 CF_D7 CF_D8 CF_D9 CF_D10 CF_D11 CF_D12 CF_D13 CF_D14 CF_D15 CF_nCD1 MA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PIN # 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NAME CF_nCD2 CF_IRQ CF_IORDY CF_nIOR CF_nIOW CF_nRESET CF_nCS0 CF_nCS1 CF_SA0 VDDIO CF_SA1 CF_SA2 SM_D0 SM_D1 VSSIO SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 SM_ALE SM_CLE SM_nRE SM_nWE SM_nWP VDDCORE SM_nCE VREG SM_nWPS SM_nB/R SM_nCD MA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PIN # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME ATEST VDDP XTAL2 XTAL1 VSSP VDDA(REF) RBIAS VSSA(REF) VDDA USB+ USBVSSA nRESET VSSCORE nTEST0 nTEST1 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6/ROMEN GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 VSSIO GPIO12 GPIO13 GPIO14 GPIO15 MA -
NAME MA0 MA1 MA2 VDDIO MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 VDDCORE MA14 MA15 MD0 MD1 MD2 MD3 VSSIO MD4 MD5 MD6 MD7 nMRD nMWR nMCE MS_INS MS_D3
-
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
8 8 8 8 8 8 8 8 8 8 8 -
Note 1: Note 2:
RBIAS is connected to the Analog Ground plane VSSA(REF) via a resistor. When the internal 1.8V regulator is enabled, VDDCORE (91) and VDDP(98), MUST have a 10uf +/- 20%, (equivalent series resistance (ESR) <0.1ohm) bypass capacitor to VSSA. VDDA(REF) and VSSA(REF) are same as the VDDA and VSSA respectively.
Note 3:
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Chapter 4
4.1
Pin Configuration
128 Pin TQFP
MA0 MA1 MA2 VDDIO MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 VDDCORE MA14 MA15 MD0 MD1 MD2 MD3 VSSIO MD4 MD5 MD6 MD7 nMRD nMWR nMCE MS_INS MS_D3
GPIO15 GPIO14 GPIO13 GPIO12 VSSIO GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6/ROMEN GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 nTEST1 nTEST0 VSSCORE nRESET VSSA USBUSB+ VDDA VSSA(REF) RBIAS VDDA(REF) VSSP XTAL1 XTAL2 VDDP ATEST
1
96
USB2224
32
64
SM_nCD SM_nB/R SM_nWPS VREG SM_nCE VDDCORE SM_nWP SM_nWE SM_nRE SM_CLE SM_ALE SM_D7 SM_D6 SM_D5 SM_D4 SM_D3 SM_D2 VSSIO SM_D1 SM_D0 CF_SA2 CF_SA1 VDDIO CF_SA0 CF_nCS1 CF_nCS0 CF_nRESET CF_nIOW CF_nIOR CF_IORDY CF_IRQ CF_nCD2
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MS_D2 MS_D1 MS_D0 MS_SCLK MS_BS SD_nWP VDDIO SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 SD_CMD SD_CLK CF_D0 CF_D1 CF_D2 CF_D3 CF_D4 VSSIO VSSCORE CF_D5 CF_D6 CF_D7 CF_D8 CF_D9 CF_D10 CF_D11 CF_D12 CF_D13 CF_D14 CF_D15 CF_nCD1
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Chapter 5
Auto address generators
Block Diagram
512 Bytes EP2 TX/RX Buffer B 512 Bytes EP2 TX/RX Buffer A 64 Bytes EP1RX 64 Bytes EP1TX 64 Bytes EP0RX EP0RX_BC Address 64 Bytes EP0TX
Flash Media DMA Unit
Address EP0TX_BC Address
1.25KB SRAM
Flash Media Controllers (FMC)
Memory Cards
CF Controller Control/ Status
Data Buss
Address MUX
EP1TX_BC
Address
32 Bit
60MHz
DATA
EP1RX_BC RAMWR_A/B
Address Address
CF
FMC Data MUX
Latch phase 0, 2 SIE
Latch phase 3 8051
Latch phase 1 FMC
DATA ECC Control/ Status SM Controller Control/ Status
RAMRD_A/B
Address Address Register
Data @ 32 bit 15Mhz
SM/SSFDC
DATA CRC
MS Controller Control/ Status SD Controller Control/ Status
MS/HS MS/MS PRO
XDATA & SFR Address and Data busses
DATA CRC
SD/HS SD/ MMC
Clocked byPhase 0, 2 Clock SIE ( Serial Interface Engine ) 32 bit 15MHz Data Buss
12K Byte Scratchpad SRAM
SIE Control Regs
USB 2.0 PHY ( Transciever )
Configuration and Control
GPIO
15 pins
Clock Generation 7 pins Interrupt Controller Osc
Scratchpad SRAM (768 Byte)
64K ROM
ROMEN
MEM/IO Bus XTAL
29pins
Program Memory/ IO Bus
FAST 8051 CPU CORE
CLOCKOUT
12 MHz
Clocked by Phase 3 Clock
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Chapter 6
Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The "n" symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "n" is not present before the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of "active low" and "active high" signal. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive.
6.1
Pin Descriptions
Table 6.1 - Pin Description NAME CF Chip Select 1 CF Chip Select 0 CF Register Address 2 CF Register Address 1 CF Register Address 0 CF Interrupt CF Data 15-8 BUFFER DESCRIPTION TYPE CompactFlash (In True IDE mode) INTERFACE CF_nCS1 O8 This pin is the active low chip select 1 signal for the CF ATA device CF_nCS0 O8 This pin is the active low chip select 0 signal for the task file registers of CF ATA device in the True IDE mode. CF_SA2 O8 This pin is the register select address bit 2 for the CF device. CF_SA1 O8 This pin is the register select address bit 1 for the CF device. CF_SA0 O8 This pin is the register select address bit 0 for the CF device. CF_IRQ IPD This is the active high interrupt request signal from the CF device. CF_D[15:8] I/O8 The bi-directional data signals CF_D15-CF_D8 in True IDE mode data transfer. The bi-directional data signal has an internal weak pull-down resistor. CF_D[7:0] I/O8 The bi-directional data signals CF_D7-CF_D0 in the True IDE mode data transfer. SYMBOL In the True IDE Mode, all of task file register operation occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. The bi-directional data signal has an internal weak pulldown resistor. This pin is active high input signal from CF card. This card detection pin is connected to the ground on the CF device, when the CF device is inserted. This card detection pin is connected to ground on the CF device, when the CF device is inserted.
CF Data7-0
IO Ready CF Card Detection2 CF Card Detection1
CF_IORDY CF_nCD2 CF_nCD1
IPU IPU IPU
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NAME CF Hardware Reset CF IO Read CF IO Write Strobe SM Write Protect SM Address Strobe SM Command Strobe SM Data7-0 SM Read Enable SM Write Enable SM Write Protect Switch SM Busy or Data Ready
SYMBOL CF_nRESET CF_nIOR CF_nIOW
BUFFER TYPE O8
DESCRIPTION
SM_nWP SM_ALE SM_CLE SM_D[7:0] SM_nRE SM_nWE SM_nWPS SM_nB/R
This pin is an active low hardware reset signal to CF device. O8 This pin is an active low read strobe signal for CF device, when the CFC is enabled. O8 This pin is an active low write strobe signal for CF device, when the CFC is enabled. SmartMedia INTERFACE O8 This pin is an active low write protect signal for the SM device, when the SMC is enabled. O8 This pin is an active high Address Latch Enable signal for the SM device, when the SMC is enabled. O8 This pin is an active high Command Latch Enable signal for the SM device, when the SMC is enabled. I/O8 These pins are the bi-directional data signal SM_D7SM_D0, when the SMC is enabled. O8 This pin is an active low read strobe signal for SM device, when SMC is enabled. O8 This pin is an active low write strobe signal for SM device, when SMC is enabled. IPU A write-protect seal is detected, when this pin is low. I This pin is connected to the BSY/RDY pin of the SM device.
SM Chip Enable SM Card Detection MS Bus State
SM_nCE SM_nCD
MS_BS
An external pull-up resistor is required on this signal. The pull-up resistor should be attached to the power of SM/NAND flash device. O8 This pin is the active low chip enable signal to the SM device. IPU This is the card detection signal from SM device to indicate if the device is inserted. MEMORY STICK INTERFACE O8 This pin is connected to the BS pin of the MS device. It is used to control the Bus States 0, 1, 2 and 3 (BS0, BS1, BS2 and BS3) of the MS device. This pin is a bi-directional data signal for the MS device. Most significant bit (MSB) of each byte is transmitted first by either MSC or MS device. The bi-directional data signal has an internal weak pulldown resistor. This pin is a bi-directional data signal for the MS device. The bi-directional data signal has an internal weak pulldown resistor that is internally controlled. This pin is a bi-directional data signal for the MS device. The bi-directional data signal has an internal weak pulldown resistor. This pin is the card detection signal from the MS device to indicate, if the device is inserted.
MS System Data In/Out
MS_SDIO /MS_D0
I/O8
MS System Data In/Out
MS_D1
IO8PD
MS System Data In/Out
MS_D[3:2]
I/O8
MS Card Insertion
MS_INS
IPU
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NAME MS System CLK SD Data3-0 SD Clock SD Command SD Write Protected USB Bus Data USB Transceiver Bias Analog Test
SYMBOL MS_SCLK
BUFFER TYPE O8
DESCRIPTION This pin is an output clock signal to the MS device.
SD_DAT[3:0] SD_CLK SD_CMD SD_nWP
USBUSB+ RBIAS
SD INTERFACE These are bi-directional data signals. This is an output clock signal to SD/MMC device. This is a bi-directional signal that connects to the CMD signal of SD/MMC device. IPD This pin is Write Protect Switch input signal with an internal weak pull-down. USB INTERFACE IO-U These pins connect to the USB bus data signals. I/O8 O8 I/O8 I A 12.0K 1% resistor is attached from ground to this pin to set the transceiver's internal bias currents. This signal is used for testing the analog section of the chip and should be connected to VDDA for normal operation. 1.8v Analog Power This pin MUST have a 10uf +/- 20%, (equivalent series resistance (ESR) <0.1ohm) bypass capacitor to VSSA. This capacitor should be placed as close to the pin as possible. Analog Ground Reference for 1.8v Analog power. 3.3v Analog Power Analog Ground Reference for 3.3v Analog Power. This pin is connected to 3.3v.
ATEST
IOA
1.8v Analog Power
VDDP
Analog Ground Reference 3.3v Analog Power Analog Ground Reference 1.8v Voltage Regulator for USB PHY Crystal Input/External Clock Input
VSSP VDDA VSSA VREG
XTAL1/ CLKIN
ICLKx
12Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 12Mhz clock when a crystal is not used. 12Mhz Crystal
Crystal Output
XTAL2
OCLKx
Memory Data Bus
MD[7:0]
This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. MEMORY/IO INTERFACE IO8 When using external program memory, these signals are used to transfer data between the internal CPU and the external program memory. When using internal program ROM, internal weak pull up resistors are activated to prevent these pins from floating.
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NAME Memory Address Bus Memory Read Strobe Memory Read Strobe Memory Chip Enable
SYMBOL MA[15:0] nMWR nMRD nMCE
BUFFER TYPE O8 O8 O8 O8
DESCRIPTION These signals address memory locations within the external memory. Program Memory Write; active low Program Memory Read; active low Program Memory Chip Enable; active low. This signal is asserted, when the device is not is SUSPEND mode. Note: This signal is held in a logic `high' state (inactive) during nRESET assertion.
GPIO6, ROMEN and RXD
GPIO6 /ROMEN
I/O8PU
MISC This pin has an internal weak pullup resistor that can be enabled or disabled by the state of nRESET. The pullup is enabled when nRESET is active. The pullup is disabled, when the nRESET is inactive (some clock cycles later, after the rising edge of nRESET). The state of this pin is latched internally on the rising edge of nRESET to determine if internal or external program memory is used. The state latched is stored in ROMEN bit of GPIO_IN1 register. After the rising edge of nRESET, this pin may be used as GPIO6 or RXD. When pulled low via an external weak pulldown resistor, an external program memory should be connected to the memory data bus. The USB2224 uses this external bus for program execution. When this pin is left unconnected or pulled high by a weak pullup resistor, the USB2224 uses the internal ROM for program execution. This pin's function while operating from internal ROM is shown in Table 6.3 - GPIO Usage. This pin may be used either as input, edge sensitive interrupt input, or output. This pin's function while operating from internal ROM is shown in Table 6.3 - GPIO Usage. This pin may be used either as input, edge sensitive interrupt input, or output. This pin's function while operating from internal ROM is shown in Table 6.3 - GPIO Usage. This pin may be used either as input, edge sensitive interrupt input, or output. This pin's function while operating from internal ROM is shown in Table 6.3 - GPIO Usage.
General Purpose I/O
GPIO1
I/O8
General Purpose I/O
GPIO2
I/O8
General Purpose I/O
GPIO3
I/O8
SMSC USB2224
Page 13
Revision 1.3 (09-21-04)
DATASHEET
Bus Powered USB2.0 Flash Media Controller Datasheet
NAME General Purpose I/O
SYMBOL GPIO4
BUFFER TYPE I/O8
DESCRIPTION This pin may be used either as input, edge sensitive interrupt input, or output. This pin's function while operating from internal ROM is shown in Table 6.3 - GPIO Usage. This pin may be used either as input, edge sensitive interrupt input, or output. This pin's function while operating from internal ROM is shown in Table 6.3 - GPIO Usage. This pin may be used either as input, edge sensitive interrupt input, or output. This pin's function while operating from internal ROM is shown in Table 6.3 - GPIO Usage. These pins may be used either as input, or output.
General Purpose I/O
GPIO5
I/O8
General Purpose I/O
GPIO7
I/O8
General Purpose I/O
GPIO[15:8]
I/O8
RESET input TEST Input
1.8v Digital Core Power
These pins' functions while operating from internal ROM are shown in Table 6.3 - GPIO Usage. nRESET IS This active low signal is used by the system to reset the chip. The active low pulse should be at least 1s wide. nTEST[0:1] I These signals are used for testing the chip. User should normally tie them high externally. DIGITAL POWER, GROUNDS, and NO CONNECTS VDDCORE +1.8V Core power All VDDCORE pins must be connected together on the circuit board. Pin 91 MUST have a 10uf +/- 20%, (equivalent series resistance (ESR) <0.1ohm) bypass capacitor to VSSA, and this capacitor should be placed as close to the pin as possible. +3.3V I/O power VDDCORE ground Reference
3.3v Digital I/O power VDDCORE reference ground VDDIO reference ground Note 1:
VDDIO VSSCORE
VSSIO
VDDIO ground reference
Hot-insertion capable card connectors are required for all of flash medias. It is required for SD connector to have Write Protect switch. This allows the chip to detect MMC card. nMCE is normally asserted except when the system is in standby mode.
Note 2:
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SMSC USB2224
DATASHEET
Bus Powered USB2.0 Flash Media Controller Datasheet
6.2
Buffer Type Descriptions
Table 6.2 - USB2224 Buffer Type Descriptions BUFFER I IPU IPD IS I/O8 I/OD8 O8 I/O8PU I/O8PD ICLKx OCLKx I/O-U O-U I-U OIA DESCRIPTION Input Input with controlled internal weak pull-up resistor. Input with controlled internal weak pull-down resistor. Input with Schmitt trigger Input/Output with 8mA drive Input/Open drain output ... 8mA sink Output with 8mA drive Input/Output with 8mA drive controlled weak pull-up resistor Input/Output with 8mA drive controlled weak pull-down resistor XTAL clock input XTAL clock output Analog Input/Output Defined in USB specification Analog Output Analog Input Special analog Input/Output
6.3
GPIO Usage Table
Table 6.3 - GPIO Usage NAME GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 ACTIVE LEVEL H/L H H H/L L SYMBOL ACT/DOOR EE_CS V_BUS EE_DIN/EE_DOUT/xDID SD_CD DESCRIPTION AND NOTE Media Activity LED / xD Door SW Input Serial EE PROM chip select USB V bus detect Serial EE PROM input/output and xD ID pin input SD Card Detect SW Input. In production ROM versions, this pin must always be pulled high except to indicate SD card insertion. If no SD interface is used, this pin must still be pulled high for proper operation. Int/Ext ROM select. External program memory A16 address line connect for DFU. Serial EE PROM clock output Memory Stick Card Power Control CompactFlash Card Power Control SmartMedia Card Power Control SD/MMC Card Power Control
GPIO6
H
A16 ( external ROM only ) /ROMEN EE_CLK MS Power Control CF Power Control SM Power Control SD Power Control
GPIO7 GPIO8 GPIO9 GPIO10 GPIO11
H L L L L
SMSC USB2224
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Revision 1.3 (09-21-04)
DATASHEET
Bus Powered USB2.0 Flash Media Controller Datasheet
NAME GPIO12 GPIO13 GPIO14 GPIO15
ACTIVE LEVEL H H H H
SYMBOL MS/MSPro Activity CF Activity SM/XDActivity SD/MMC Activity
DESCRIPTION AND NOTE Memory Stick(/Pro) Activity Indicator CompactFlash Activity Indicator SmartMedia/XD Activity Indicator SD/MMC Activity Indicator
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SMSC USB2224
DATASHEET
Bus Powered USB2.0 Flash Media Controller Datasheet
Chapter 7
7.1
DC Parameters
Maximum Guaranteed Ratings
Operating Temperature Range .................................................................................................. 0oC to +70oC
o o Storage Temperature Range .................................................................................................. -55 to +150 C o Lead Temperature Range (soldering, 10 seconds) .............................................................................+325 C
Positive Voltage on any pin, with respect to Ground ............................................................................... 5.5V Negative Voltage on any pin, with respect to Ground ............................................................................ -0.3V Maximum VDD, VDDP .............................................................................................................................. +2.5V Maximum VDDIO, VDDA ............................................................................................................................ +4.0V * Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Notes: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used. The name "VDD" is the same as VDDCORE
7.2
DC Electrical Characteristics
(TA = 0C - 70C, VDDIO, VDDA = +3.3 V 10%, VDD, VDDP = +1.8 V 10%,) PARAMETER I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Hysteresis VILI VIHI 2.0 0.8 V V TTL Levels SYMBOL MIN TYP MAX UNITS COMMENTS
VILI VIHI VHYSI 2.0 500
0.8
V V mV
TTL Levels
SMSC USB2224
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Revision 1.3 (09-21-04)
DATASHEET
Bus Powered USB2.0 Flash Media Controller Datasheet
PARAMETER ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O8 Type Buffer Low Output Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VILCK VIHCK 2.2
0.4
V V
IIL IIH
-10 -10
+10 +10
uA uA
VIN = 0 VIN = VDDIO
VOL
0.4
V
IOL = 8 mA @ VDDIO= 3.3V
High Output Level
VOH
2.4
V
IOH = -4mA @ VDDIO= 3.3V
Output Leakage
IOL
-10
+10
uA
VIN = 0 to VDDIO
(Note 7.1)
I/O8 Type Buffer Low Output Level VOL 0.4 V IOL = 8 mA @ VDDIO= 3.3V
HIGH OUTPUT LEVEL
VOH
2.4
V
IOH = -4 mA @ VDDIO= 3.3V
Output Leakage
IOL
-10
+10
A
VIN = 0 to VDDIO
(Note 7.1)
I/O12 Type Buffer Low Output Level VOL 0.4 V IOL = 12 mA @ VDDIO= 3.3V
High Output Level
VOH
2.4
V
IOH = -6mA @ VDDIO= 3.3V
Output Leakage
IOL
-10
+10
A
VIN = 0 to VDDIO
(Note 7.1)
Revision 1.3 (09-21-04)
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SMSC USB2224
DATASHEET
Bus Powered USB2.0 Flash Media Controller Datasheet
PARAMETER I/O24 Type Buffer Low Output Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL
0.4
V
IOL = 24 mA @ VDDIO= 3.3V
High Output Level
VOH
2.4
V
IOH = -12 mA @ VDDIO= 3.3V
Output Leakage IO-U Supply Current Unconfigured
IOL
-10
+10
A
VIN = 0 to VDDIO
(Note 7.1)
ICCINIT
45 10 35 15 45 15 160 215
60 20 60 30 70 30 180 240
mA mA mA mA mA mA A A
Supply Current Active (Full Speed) Supply Current Active (High Speed) Supply Current Standby
ICC
ICC
ICSBY
@ VDD, VDDP = 1.8V @ VDDIO, VDDA = 3.3V @ VDD, VDDP = 1.8V @ VDDIO, VDDA = 3.3V @ VDD, VDDP = 1.8V @ VDDIO, VDDA = 3.3V @ VDD, VDDP = 1.8V @ VDDIO, VDDA = 3.3V
Note 7.1 Output leakage is measured with the current pins in high impedance.
CAPACITANCE TA = 25C; fc = 1MHz; VDD, VDDP = 1.8V LIMITS PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SYMBOL CIN CIN COUT MIN TYP MAX 20 10 20 UNIT pF pF pF TEST CONDITION All pins except USB pins (and pins under test tied to AC ground)
SMSC USB2224
Page 19
Revision 1.3 (09-21-04)
DATASHEET
Bus Powered USB2.0 Flash Media Controller Datasheet
Chapter 8
Package Outline
Figure 8.1 - 128 Pin TQFP Package MIN ~ 0.05 0.95 15.80 13.80 15.80 13.80 0.09 0.45 ~ Table 8.1 - 128 Pin TQFP Package Parameters NOMINAL MAX REMARKS ~ 1.20 Overall Package Height ~ 0.15 Standoff ~ 1.05 Body Thickness ~ 16.20 X Span ~ 14.20 X body Size ~ 16.20 Y Span ~ 14.20 Y body Size ~ 0.20 Lead Frame Thickness 0.60 0.75 Lead Foot Length 1.00 ~ Lead Length 0.40 Basic Lead Pitch ~ 7o Lead Foot Angle 0.18 0.23 Lead Width ~ ~ Lead Shoulder Radius ~ 0.20 Lead Foot Radius ~ 0.08 Coplanarity
A A1 A2 D D1 E E1 H L L1 e o 0 0.13 W 0.08 R1 0.08 R2 ~ ccc Notes: 1) Controlling Unit: millimeter. 2) Tolerance on the true position of the leads is 0.035 mm maximum. 3) Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4) Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5) Details of pin 1 identifier are optional but must be located within the zone indicated.
Revision 1.3 (09-21-04) Page 20
SMSC USB2224
DATASHEET

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